High-performance analog circuits are usually implemented in discrete-time circuits, often as switched capacitor (SC) circuits. In a typical circuit architecture, switched capacitors are often integrated because of their small area and high speed. Inherent errors of the capacitors and switches, however, can limit the linearity performance of such circuits. Generally incorporated with an analog-to-digital converter (ADC), these structures can achieve high resolution conversion for low frequency signals, such as Sigma Delta converters.
The inherent errors in conventional SC structures are mainly due to three reasons: charge injection, non-linearity of CMOS switches and capacitor mismatching. Therefore, a tradeoff is often made with respect to speed, accuracy, power consumption and design flexibility. In addition, noise contribution from power supplies should be minimized. Since fully differential circuits have a high common mode rejection, noise contribution from power supplies is an issue for single-ended structures. Nevertheless, fully differential structures require fully differential amplifiers with common mode feedback circuitry to center the output signals around the common mode level of the system. This part of the structure can be challenging to design for high-speed discrete-time operations.
One design technique used to perform single ended to fully differential conversion is the charge and transfer technique (also called charge-redistribution). In charge and transfer designs, analog input voltages are sampled into sampling capacitors in a first phase, then transferred to integration capacitors in a second phase. In a third phase, the integration capacitors are discharged (reset), thus ready to hold the next sampled charges. This design can operate as a simple sample and hold circuit and as an integrator if the feedback capacitors are not reset in each phase. This property is used in oversampling ADCs such as Sigma Delta converters which perform noise shaping to achieve high resolution conversions.
There exist conventional circuits which are capable of providing single ended to fully differential conversions. Some of these conventional circuits require high oversampling which limits the input bandwidth. Other conventional circuits only use positive input and shunt negative input to ground. Therefore, noise immunity (kT/C) and capacitor matching accuracy can differ from one mode to the other.
Other conventional circuits use only the one capacitor (or one branch of the sampling structure) to sample the input, thus, KT/C is double. Moreover, the transfer function for single ended conversion is different than the transfer function for fully differential conversion.